Protecting integrity of data in multi-layered memory with data redundancy

ABSTRACT

Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.

FIELD OF THE INVENTION

Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for multi-layered memory protection with data redundancy implementing, for example, third dimensional memory technology.

BACKGROUND OF THE INVENTION

Traditional storage technologies, such as hard disk drive technologies (HDD), have used memory protection techniques to preserve file directories and access pointer systems, including file allocation tables (FATs) such as the kind used in a computer software operating system, such as the Disk Operating Systems (DOS), for example. Those pointers, directories, and tables are very valuable data which might be lost in the event of a system failure. In that some data is more important than other data, it is important to protect important data in the event of a system failure, a HDD crash, or the like. In some applications, user data is also important and needs to be protected. Further, protection of data in some storage systems requires reliable hardware components that remain resilient throughout extensive usage. Regardless, in a HDD a head media failure (“head crash”), once it occurs, is a catastrophic failure that is usually irrecoverable. Therefore, there are data redundancy issues and concerns that must be addressed in order to provide data protection.

Some of the approaches to memory protection have been applied to non-volatile memory, such as flash memory, which can provide a higher data storage density at a lower cost. However, using flash memory has a few drawbacks. First, flash memory typically performs an erase operation prior to any write operation. Second, additional circuitry is required to implement the erase operation. The additional circuitry increases die area and the cost per bit. Third, flash memory usually requires additional file management software that must be mapped on top of the standard file management structure in order to perform the erase operation (e.g., a block erase operation).

As non-volatile memory technologies continue to encroach into the data storage arena and displace traditional HDD's in applications such as RAID systems and solid state drives (SSD's), it is desirable to implement data redundancy in non-volatile memory and to eliminate the latency created by the erase before write operation and its associated file system overhead (e.g., FLASH OS).

There are continuing efforts to improve data redundancy technology for protecting data stored in memory.

BRIEF DESCRIPTION OF THE DRAWINGS

Various examples are disclosed in the following detailed description and the accompanying drawings, in which:

FIG. 1 depicts an apparatus implementing a redundancy circuit configured to duplicate data associated with multiple layers of memory;

FIG. 2 is a block diagram depicting an example of a redundancy circuit;

FIG. 3A depicts a cross-sectional view of an example of an integrated circuit implementing a redundancy circuit;

FIG. 3B depicts a cross-sectional view of another example of an integrated circuit implementing a redundancy circuit;

FIG. 3C depicts a cross-sectional view of yet another example of an integrated circuit implementing a redundancy circuit;

FIG. 4 is a diagram depicting a cross-sectional view of a partial duplication for use with a redundancy circuit;

FIG. 5A is a block diagram depicting one example of an integrated circuit implementing a redundancy circuit;

FIG. 5B is a block diagram depicting one example of an integrated circuit implementing data redundancy in a third dimensional memory array with specific memory planes allocated for storing read data and different memory planes allocated for storing copy data;

FIG. 5C is a block diagram depicting one example of an integrated circuit implementing full data redundancy in different planes of a third dimensional memory array;

FIG. 6 depicts an illustration of an exemplary parity module;

FIG. 7A depicts an example of memory cells positioned in a two-terminal cross-point array;

FIG. 7B depicts a single layer or multiple vertically stacked layers of memory arrays formed BEOL on top of a base layer die including circuitry formed FEOL;

FIG. 7C depicts one example of a vertically stacked memory including multiple array layers that share conductive array lines and formed BEOL directly on top of a previously formed FEOL base layer;

FIG. 8A depicts a cross-sectional view of an integrated circuit die including a single layer of memory fabricated over a substrate including active circuitry fabricated on the substrate in a logic layer;

FIG. 8B depicts a cross-sectional view of an integrated circuit die including vertically stacked layers of memory fabricated over a substrate including active circuitry fabricated on the substrate in a logic layer;

FIG. 8C depicts an integrated circuit die including vertically stacked layers of memory with shared conductive array lines fabricated over a substrate including active circuitry fabricated on the substrate in a logic layer;

FIG. 9 depicts a memory system including a non-volatile two-terminal cross-point array;

FIG. 10 depicts an exemplary electrical system that includes at least one non-volatile two-terminal cross-point array; and

FIG. 11 depicts top plan views of a wafer processed FEOL to form a plurality of base layer die including active circuitry and the same wafer subsequently processed BEOL to form one or more layers of memory directly on top of the base layer die where the finished die can subsequently be singulated, tested, and packaged into integrated circuits.

Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGS. are not necessarily to scale.

DETAILED DESCRIPTION

U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, entitled “Memory Using Mixed Valence Conductive Oxides,” and published as U.S. Pub. No. US 2006/0171200 A1 on Aug. 3, 2006, is herein incorporated by reference in its entirety and for all purposes, and describes non-volatile third dimensional memory elements that may be arranged in a two-terminal, cross-point memory array. The memory elements can be a component of a memory cell that includes electrically in series with the memory element, other structures including but not limited to a non-ohmic device (NOD) and electrodes. New non-volatile memory structures are possible with the capability of this third dimensional memory array. The technology allows for the emulation of other memory technologies by duplicating the interface signals and protocols, while accessing the third dimensional memory array. The third dimensional memory array may emulate other types of memory (e.g., DRAM, SRAM, FLASH, and ROM), providing memory combinations (e.g., DRAM, FLASH, and SRAM) within a single component. In at least some embodiments, a two-terminal memory cell can be configured to change conductivity when exposed to an appropriate voltage drop across the two-terminals. The memory cell can include an electrolytic tunnel barrier and a mixed valence conductive oxide (e.g., a memory element) in some embodiments, as well as multiple mixed valence conductive oxide structures in other embodiments. A voltage drop across the electrolytic tunnel barrier can cause an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide, according to some embodiments.

In some embodiments, an electrolytic tunnel barrier and one or more mixed valence conductive oxide structures do not need to operate in a silicon substrate, and, therefore, can be fabricated (e.g., back-end-of-the-line BEOL) above circuitry being used for other purposes (e.g., circuitry fabricated front-end-of-the-line FEOL). The circuitry portion of an IC can be fabricated FEOL on a substrate (e.g., a silicon Si wafer) that is partitioned into die with each die forming the base structure for the IC. After the FEOL processing is completed the substrate is processed BEOL to fabricate the one or more layers of memory directly on top of each FEOL die. An inter-level interconnect structure formed FEOL serves as the structural and electrical foundation for the subsequent formation of the one or more layers of memory that will be deposited (e.g., formed) on top of the FEOL die. The inter-level interconnect structure includes vias, plugs, damascene structures or the like, that allow the FEOL circuitry to be electrically coupled with the BEOL memory layer(s). After BEOL processing is completed, the finished die can be singulated from the substrate (e.g., removed by sawing or cutting) to form individual die that can be inserted into a suitable package and electrically coupled with bonding pads or other structures in the package to form an integrated circuit (IC). Therefore, each die is an integral unit that includes at a bottommost layer the FEOL circuitry and upper layers comprised of one or more layers of third dimensional memory that are positioned above the FEOL circuitry layer. Unlike conventional IC's that have conventional memory (e.g., SRAM, DRAM, and FLASH) fabricated FEOL on the same substrate die as the circuitry that accesses the memory such that the memory and the circuitry are disposed on the same physical plane, the BEOL third dimensional memory layer(s) are not on the same plane as the FEOL circuitry and therefore do not take up area on the FEOL die. Accordingly, data storage can be increased without increasing the area of the FEOL die by fabricating additional BEOL memory layers on top of the FEOL die (e.g., along the +Z axis of FIGS. 7B-8C).

Further, a two-terminal memory cell can be arranged in a cross-point configuration such that one terminal is electrically coupled with an X-direction line (or an “X-line”) and the other terminal is electrically coupled with a Y-direction line (or a “Y-line”). A third dimensional memory can include multiple memory cells vertically stacked upon one another, sometimes sharing X-direction and Y-direction lines in a layer of memory, and sometimes having electrically isolated X and Y direction lines (e.g., using a dielectric material such as SiO₂). When a first write voltage, VW1, is applied across the memory cell (e.g., by applying ½ VW1 to the X-direction line and ½-VW1 to the Y-direction line), the memory cell can switch to a low resistive state. When a second write voltage, VW2, is applied across the memory cell (e.g., by applying ½ VW2 to the X-direction line and ½-VW2 to the Y-direction line), the memory cell can switch to a high resistive state. Memory cells using electrolytic tunnel barriers and mixed valence conductive oxides can have VW1 opposite in polarity from VW2. The optional NOD is operative to substantially block current flow through the memory cells that are half-selected or un-selected, that is for memory cells that do not have a read voltage or a write voltage applied across their terminals.

FIG. 1 illustrates an apparatus implementing a redundancy circuit configured to duplicate data associated with memory cells disposed in multiple layers of memory, according to one or more embodiments of the invention. Apparatus 100 includes a memory array 110 including multiple layers 116 of memory formed in planar fashion (e.g., directly on top of each other in the +Z direction), a redundancy circuit 120, and a logic layer 119. Although depicted separated from one another for purposes of illustration, the logic layer 119 and multiple layers 116 of memory are connected with one another to form a unitary structure (e.g., a die) as will be discussed below in regards to FIGS. 3A-11. Redundancy circuit 120 can be configured to duplicate a data 102 (or a portion thereof) and place a copy of the data 102 separately within memory array 110. As shown, redundancy circuit 120 can be configured to protect data (or portion thereof) within memory array 110 by generating redundant data for use as a substitute should the data become compromised. Also, redundancy circuit 120 can include a control module 121 and an error detection module 122, each including a portion of logic from logic layer 119 to perform data duplication. For example, control module 121 can be configured to map at least two memory cells disposed within separate memory layers of memory array 110, each forming subset 117 and subset 118.

To illustrate, control module 121 can include a list of addresses (e.g., lookup table, pointers, offsets, or others), in which each address can be associated to a memory cell within memory array 110. As such, the list of address can constitute a group of memory cells, which can form either subset 117 or subset 118.

As used herein, the term “map” refers generally, to an association between a memory location and an address. For example, a subset can be any volume that includes memory cells in, for example, a portion of a layer in at least one of multiple layers 116 of memory. In at least some examples, a subset can refer to a group of one or more layers, sub-planes, or like subdivisions of memory. In at least some embodiments, redundancy circuit 120 can store duplicate data in any subset of multiple layers 116 of memory. In still other examples, either subset 117 or subset 118 can be configured to contain half (or substantially half) of the storage capacity for memory array 110. As one example, if the storage capacity for the memory array 110 is 16 GB, then approximately 8 GB can be allocated to subset 117 and approximately 8 GB can be allocated to subset 118. If the entire chip is used to duplicate the entire data to be stored, then the chip will be acting as a RAID 1 storage device the makes copies of all files.

In some examples, at least one memory cell of subset 117 can reside in a different layer within memory array 110 from at least one memory cell associated with subset 118. Note while that subset 117 includes four layers as does subset 118, that not have to be the case in other examples (e.g., both subset 117 and subset 118 can be disposed in the same layer, which is not shown). Further, redundancy circuit 120 can be configured to write to at least two subsets within memory array 110, in parallel (or substantially in parallel). To illustrate, redundancy circuit 120 can send data 123 containing data 102 (e.g., write data) to subset 117, which can be assigned by control module 121. Control module 121 can map a subset within memory array 110 using address 101 to construct subset mapping 125, for example, a compilation of memory addresses, which can form subset 117. Further, the compilation of memory addresses handled by control module 121 can be configured to identify portions of memory dedicated to store a type of data (e.g., copied data 124). Also, the same can be done for subset 118, whereby subset mapping 126 can follow a similar procedure to assign another subset for the copied data 124. Here, subset mappings 125 and 126 are conceptually depicted, for purposes of illustration, as a portion of the memory cells disposed in the uppermost layers of subsets 117 and 118 respectively. However, the subset mappings 125 and 126 can be implemented in a variety of ways and are not limited to the arrangement depicted in FIG. 1. For example, the subset mappings 125 and 126 need not reside in the same layer as depicted. Subsequently, subset 118 can receive data 102 from redundancy circuit 120. In other examples, redundancy circuit 120 can include decoding hardware that can be associated with at least one memory layer of memory array 110. To illustrate, a set of decoders (not shown) can be assigned to access subset 117 and another set of decoders can be assigned to access subset 118. Further, each subset mapping (e.g., subset mapping 125, subset mapping 126) can contribute to a standard file management structure, in connection with, software handling the complete duplication (or partial duplication). In still other examples, error detection module 122 can be configured to detect a mismatch between at least a portion of write data 102 and the copy of the portion of write data 102 disposed within multiple layers of memory, including but not limited to, the same memory layer, as well as separate memory layers. For example, error detection module 122, in connection with, comparison module 129, in which both can compare two sets of data including subset 127 and subset 128, and determine whether, for example, subset 128 contains a replica of subset 127. To illustrate, error detection module 122 retrieves read data 112 containing subset 127, which constitutes data of subset 117 denoted to be original data, and can use comparison module 129 to compare it to retrieved read data 114 containing subset 128, which constitutes data of subset 118 denoted to be copied data. As such, comparison module 129 can be configured to use algorithmic hash functions to detect or correct, for example, mismatched bits of data. In some examples, the term “duplicated” refers generally, to the term “copied,” and may be used interchangeably. In other examples, error detection module 122 can be configured to instruct redundancy circuit 120 to forward data out of apparatus 100, in which a matched data comparison was determined. As used herein, the term “layer” refers generally, to a flat, conceptual surface passing containing, for example, the X and Y axes, the Y and Z axes, or the Z and X axes, as well as any similar surface that is parallel to any of the aforementioned axes. In still other examples, the term “layer” refers generally, to the term “plane,” and may be used interchangeably. In some examples, control module 121 can be configured as a controller for redundancy circuit 120, and therefore, provide control for the data redundancy operations.

In view of the foregoing, apparatus 100 can include subset 118 in memory array 110 to store copied data without increasing the die size of, for example, logic plane 119 or the substrate (not shown) upon which logic plane 119 is formed. For example, logic layer 119 can be a silicon wafer upon which active circuitry has been fabricated (e.g., CMOS devices) for performing data operations (e.g., read and write operations on one or more layers of memory) as part of a front-end-of-the-line (FEOL) fabrication process. The one or more layers of memory 116 can be fabricated directly on top of the logic layer 119 as part of a back-end-of-the-line (BEOL) fabrication process such that at the end of all processing, that is both FEOL processing and BEOL processing, the layers 119 and 116 form a single unitary die (e.g., die 800 in FIG. 11). The die can subsequently be removed from the wafer (e.g., singulated) and inserted into a suitable package for an IC, for example. The FEOL and BEOL processes can occur at the same or different fabrication facilities and the same or different vendors may perform the FEOL and BEOL processes. Specifically, adding memory to store copied data in multiple layers 116 of memory affects the Z dimension (e.g., along the +Z axis) of apparatus 100 rather than the X and Y dimensions. As such, implementation of multiple layers of memory to store copied data can facilitate data backup (or recovery) without increasing the die size to include redundancy circuit 120 in logic plane 119.

Further, redundancy circuit 120 can collaborate with third dimensional memories, which can have relatively small sizes and fast access times, to access memory cells of subset 117 and subset 118 in parallel (or substantially in parallel), to the access of either subset 127 or subset 128. As such, there can be no noticeably different (or substantially negligible) time delays when accessing memory cells in subset 117 or subset 118. Additionally, parallel access to memory array 110 can facilitate expeditious duplication of memory cells, which otherwise might not be the case. As used herein, the term “access” refers generally, to a write operation (e.g., writing data 102), a read operation (e.g., reading stored data 112 or 114), or any other memory operation, which can be an action resulting from a single memory instruction such as the read or the write. Writing data can be accomplished through a program instruction that writes one or more memory cells to a high resistance state indicative of logic “0” and an erase instruction that writes one or more memory cells to a low resistance state indicative of logic “1”. Actual conventions for logic states and there associated resistance or conductivity (e.g., program or erase) will be application dependent and in some implementations an erased memory cell can be indicative of logic “0” and a programmed cell indicative of a logic “1”. Herein, for purposes of explanation, the programmed state will be indicative of logic “0” and a high resistance state and an erased state will be indicative of logic “1” and a low resistance state. During a read operation data stored in the programmed cells can be sensed as a first read current (e.g., a low read current due to the high resistance of programmed cells); whereas, data stored in the erased cells can be sensed as a second read current (e.g., a high read current due to the low resistance of erased cells). Here, unlike conventional FLASH based non-volatile memory, a write operation to the array 110 does not require a preceding erase operation (e.g., a block erase operation). A write operation is the act of changing the resistance of one or more selected memory cells based on a voltage difference applied across the terminals of the selected memory cell(s).

FIG. 2 is a block diagram illustrating an example of a redundancy circuit, according to one or more embodiments of the invention. Here, diagram 200 shows a redundancy circuit 202, a control module 204, and an error detection module 206. In some examples, redundancy circuit 202 can be configured to perform a series of operations, including but not limited to, writing to a subset (e.g., subset 117 (FIG. 1)) in parallel to writing to another subset (e.g., subset 118 (FIG. 1)), reading from multiple subsets in parallel, checking data after each read operation using parity (or any other detection technique), and recovering data after a detected redundancy failure. In other examples, redundancy circuit 202 can be configured to delay write operations containing copied data to, including but not limited to, a single memory layer or multiple memory layers. To illustrate, redundancy circuit 202 can organize each write operation as mentioned in sequential order, and can maintain data redundancy with the inclusion of an error detection performed by error detection module 206 following the write operation.

Here, redundancy circuit 202 can be configured to duplicate a unit of data (i.e., a datum) determined by control module 204, in connection with, address 210. As described above, control module 204 can be configured to include decoding hardware, such as decoders 205, which can translate address 210 and access a portion of memory (e.g., subset 117). In some examples, control module 204 can partition layers of memory array 110 (FIG. 1) into subsets (e.g., subset 117, subset 118) using memory mapping signal 222, which can provide these subsets with identifiers using address 210 (or pre-determined by an external software program). After partitioning the memory layer, memory mapping signal 222 can map these partitioned layers into contiguous locations of memory (i.e., connecting without a break, within a common boundary) to form a block (or area) of memory. In other examples, these partitioned layers can be non-contiguous, with the addition of extra circuitry to manage any addressing in forming the block. Further, redundancy circuit 202 can be configured to write data in parallel (or in serial) to multiple memory layers, for example, to subset 117 (FIG. 1) and subset 118 (FIG. 1). In one example, original data write 224 can be configured to provide write data 211 to subset 117 (FIG. 1), in which can be provided in parallel to, (or substantially in parallel to), copied data write 226, whereby copied data write 226 can be configured to provide another portion of write data 211 to subset 118 (FIG. 1). In another example, original data write 224 can be provided before (i.e., sequentially earlier) copied data write 226, resulting in a delayed data redundancy check.

Further, redundancy circuit 202 can be configured to perform error detection (i.e., comparing the condition of a number of bits in a set of data, used as a means for detecting certain errors) to the data read from memory array 110 (FIG. 1). To illustrate, parity module 206 can be configured to retrieve multiple sets of data in parallel (or substantially in parallel) to perform a comparison between the sets of data. Moreover, the multiple sets of data can be portions of data retrieved from a subset, such as subset 128 (FIG. 1). In some examples, redundancy circuit 202 can access (e.g., perform a read operation) memory array 110 (FIG. 1) following any write operation, in connection with, error detection module 206. In this example, error detection module 206 can perform the comparison to determine a mismatch between original data read 212 and copied data read 214. If there is a mismatch, error detection module 206 can provide mismatch signal 216 to divert data diverter 207 to recover copied data read 214. After the mismatch, recovery signal 218 can instruct control module 204 to perform an additional write operation (i.e., a reduplication) to each subset, including but not limited to, subset 117 (FIG. 1) and subset 118 (FIG. 1), and perform an additional error detection verifying the protection of the original data (e.g., subset 127). In other examples, data diverter 207 can forward error flag 220 to provide an alert signal to a data port (not shown) denoting a mismatch has been detected. In still other examples, redundancy circuit 202 can bypass a read operation following any write operation determined by a wait-state generator (not shown). For example, as part of a recovery operation and/or the recovery signal 218 going active, the redundancy circuit 202 can be configured to write wait-state data to a memory plane configured to store the wait-state data. As one example, the aforementioned wait-state is given to the interface to stall activity while a prolonged write operation or a write operation followed by a read operation is occurring. Further, redundancy circuit 202 can be configured to forward any read data, such as forward read data signal 221, including an option to select between original read data 212 and copied data read 214. Also, error flag signal 220 can accompany forward read data signal 221 to the data port. As used herein, the term “partitioned layer” refers generally, to an amount of storage needed to support a computational resource, such as data redundancy. In some examples, diagram 200 and the above-described elements (i.e., all elements shown and indicated by reference numerals above) can be implemented differently in design, operation, and configuration, and are not limited to the descriptions provided herein.

FIG. 3A depicts a cross-sectional view of an example of an integrated circuit implementing a redundancy circuit, according to one or more embodiments of the invention. Here, cross-sectional view 300 includes memory planes 302 formed BEOL along the +Z axis, and a redundancy circuit 320 and a logic layer 330 formed FEOL along the −Z axis. Cross-section view 300 shows multiple memory planes being vertically disposed above and in contact with logic layer 330 (e.g., fabricated BEOL directly on the logic layer 330), which can include logic circuitry for implementing data redundancy, and a semiconductor substrate upon which the logic circuitry can be formed (e.g., using CMOS fabrication technology). As shown in this example, redundancy circuit 320 can be configured to include error detection module 322 and control module 324. In some examples, control module 324 can be configured to map at least two memory cells being disposed on separate memory layers to form subset 312 and subset 314. To illustrate, subset 312 can include memory layer 302 a and memory layer 302 b, including but not limited to, more or less memory layers. Also, subset 314 can include memory layer 302 c and memory layer 302 d, including but not limited to, more or less memory layers, to provide a subset (e.g., subset 118 (FIG. 1)) for copied data. As such, parity module 322 can be configured to detect a mismatch between a portion of data and a copy of the portion of the data disposed in separate memory layers. Further, control module 324 can be configured to, but not limited to, partitioning memory layers 302, allocating portions of each partition with a type of data, such as original data or copied data, and map addresses to each partition. Also, redundancy circuit 320 can be configured to perform parity checks (e.g., a comparison of data to find errors using the error detection module 322) among a single layer or multiple layers of memory, containing data from subset 312 and subset 314 (or a portion thereof).

Multiple memory layers can include contiguous blocks (or areas) of memory having a portion of an original set of data and a copy of the portion of the original set of data. To illustrate, subset 314 can be configured to include data of the same type (e.g., copied data) independent of any separation by layers with another type of data (e.g., original data). Note that subset 312 and subset 314 can be associated with other memory layers or sub-layers, and therefore, need not be restricted to first original data area memory layer 302 a and first copied data area memory layer 302 c, respectively. Also, Nth original data area memory layer 302 b can include third dimensional memory cells for an Nth array.

FIG. 3B depicts a cross-sectional view of another example of an integrated circuit implementing a redundancy circuit, according to one or more embodiments of the invention. As shown in this example, cross-sectional view 350 can be configured to include multiple memory layers with non-contiguous blocks of data. For example, subset 314 can be described by multiple layers of memory (e.g., along the +Z axis), including but not limited to, memory layer 352 b, memory layer 352 d, and memory layer 352 f. Similarly, subset 312 can be configured to include memory layer 352 a, memory layer 352 c, and memory layer 352 e. As such, each memory layer of a subset is separated by at least one other memory layer of the other subset. Also, each memory layer can be accessed independently of each other memory layer, thus providing the possibility to access at least two memory layers simultaneously (or substantially simultaneously).

FIG. 3C depicts a cross-sectional view of yet another example of an integrated circuit implementing a redundancy circuit, according to one or more embodiments of the invention. As shown in this example, cross-sectional view 380 can be configured to include multiple memory layers 382 with partial contiguous blocks of data. To illustrate, first memory layer 382 a can contain copied data area 392 and original data area 394, which continues into second memory layer 382 b of third dimensional memory cells. As such, each subset (e.g., a data area) can be configured to be accessed independently, and simultaneously (or substantially simultaneously), in accordance with, redundancy circuit 320. In other examples, the multiple memory planes shown in cross-section view 380 can include more or fewer layers than as shown in FIG. 3C, any of which can emulate other types of memory technologies (e.g., DRAM, SRAM, FLASH, HDD).

An example of an alternate implementation would be to have the original and copy segments in different planes with the area outside the copy area being available as continuation of the original data area. It should be pointed out that the control module will interact with non-volatile configuration bits. These configuration bits will be used to assign mapping between memory planes. A portion of one or more memory planes can be allocated (e.g., reserved) for storing the non-volatile configuration bits. For example, an address of data to access data in plane 0 can be configured to access data in other planes such as plane 3. In this example a write operation and read operation of plane 0 would result in the simultaneous access of the plane 3 memory area. Using the configuration bits, the mapping of copy data can be turned on and off and can be used to identify where the copy area is for copy enabled data areas. It should be further noted that partial plane copying can be activated such that data written to part of plane 0, as an example, is also written to plane 3, once the data gets outside the address range selected for copying, the memory switches to storing only at the selected location with no copy activity. It should also be noted that configuration bits used for setting the steering logic is well understood by those skilled in the art and has been used for years in memory technology.

FIG. 4 is a diagram depicting a cross-section view of a partial duplication for use with a redundancy circuit, according to one or more embodiments of the invention. Here, diagram 400 can be configured to include multiple memory layers 402 a-f and a logic layer 410. In some examples, it can be desirable to copy only a portion of an original set of data into a specific number of layers. To illustrate, a subset (or mapped area) can be partitioned to include layers or sub-layers that can be combined to form a contiguous block of copied data. For example, memory layer 402 f (e.g., Block A) can be copied accordingly into memory layer 402 b. As such, memory layer 402 e can be copied into memory layer 402 a. Note that memory layer 402 c and memory layer 402 d are not desired to be protected, and therefore, need not be duplicated into other memory layers. Also, note that copied data (e.g., copy of Block A, copy of Block B) can be placed in other memory layers or sub-layers, and therefore, need not be restricted to memory layer 402 a and memory layer 402 b, respectively. In other examples, copied data can increase in size (or decrease in size), and therefore, the number of memory layers needed to store the copied data can be adjusted accordingly, and are not limited to this example. Further, logic layer 410 can include logic circuitry for implementing data redundancy, and a semiconductor substrate (e.g., a silicon Si wafer) upon which the logic circuitry can be formed (e.g., using CMOS fabrication technology).

FIG. 5A is a block diagram illustrating an integrated circuit 540 implementing a redundancy circuit, according to one or more embodiments of the invention. Here, diagram 500 includes a third dimensional memory array 502 (e.g., fabricated BEOL), a row decoder 512, a column decoder 514, a gating logic 516, a column driver 518, a row driver 520, a multiplexer 532, and a sense amplifier 534. In this example, third dimensional memory array 502 can be configured to store at least two sets of data, including an original data (e.g., subset 127 (FIG. 1)) and a copied data (e.g., subset 128 (FIG. 1)). As such, third dimensional memory array 502 can be configured to be accessed simultaneously (or substantially simultaneously). In other examples, third dimensional memory array 502 can be configured to be accessed serially, including but not limited to, write operations and read operations. Third dimensional memory array 502 can be configured to accept writes to memory cells disposed in memory layers, including sub-layers, independent of any precedent erase operation, that is, an erase operation is not required prior to a write operation on the array 502. Also, third dimensional memory array 502 can be configured to accept write operations in succession, with the inclusion of read operations following a similar procedure. Here, diagram 500 depicts write data 538 entering gating logic 516, to provide a set of original data destined to be copied within third dimensional memory array 502. Column decoder 514 receives address 510 containing a mapping (i.e., address range of use) within third dimensional memory array 502, to denote at least two locations to store write data 538. This is because a copy can be made to protect write data 538 in case of a system failure, and therefore, being able to access the original data. Accordingly, at least two locations are required to redundantly store write data 538, an original data location and a copied data location. Column driver 518 can be configured to provide an appropriate amount of voltage to conduct a series of Y-lines within third dimensional memory array 502. In some examples, third dimensional memory array 502 can include a redundancy circuit (not shown) to perform the duplication of data. In other examples, elements such as, but not limited to, column decoder 514, gating logic 516, column driver 518, row driver 520, row decoder 512, sense amp 534, and multiplexer 534 can constitute the redundancy circuit, as described above. In still other examples, data can be read from third dimensional memory array 502 by detecting address 510, and translating this address using row decoder 512. Row driver 520 can be configured to use the translated (i.e., decoded) address to drive an appropriate voltage level to a selected memory cell (or memory cells) denoted by the translated address by conducting a series of X-lines within third dimensional memory array 502. In response, sense amplifier 534 receives another voltage, being the result of a resistance differential across the accessed memory cell within third dimensional memory array 502. In some examples, row decoder 512 can be configured to read from at least two memory cells in parallel (or substantially in parallel), and provide read data to a parity checker (not shown), for example, to perform a comparison, and detect any mismatch between the data disposed within the two memory cells (e.g., an original data cell and a copy data cell). Multiplexer 532 can be configured, in connection with, copy select signal 530, which can choose between the original data or copied data. Copy select signal 530 can be configured to select a value from multiplexer 532 using either a high voltage (e.g., logic value “1”, +V) or a low voltage (e.g., logic value “0”, −V). Further, read data signal 536 can be forwarded from multiplexer 532 to a data port (not shown) independent of any subsequent read operation or write operation. Note that specific elements, including but not limited to, column decoder 514, gating logic 516, row decoder 512, row driver 520, column driver 518, sense amp 534, and multiplexer 532, can be configured to be duplicated on the basis of the number of data duplications needed to protect the original data. As such, if only one duplicate is needed to protect the original data, then only one duplicate of these elements can be implemented. In some examples, diagram 500 and the above-described elements (i.e., all elements shown and indicated by reference numerals above) can be implemented differently in design, operation, and configuration, and are not limited to the descriptions provided herein. Some or all of the circuitry elements depicted in FIGS. 5A-5C (e.g., column decoders, gating logic, row decoders, row drivers, column drivers, sense amps, and multiplexers, etc.) can be implemented as FEOL circuitry fabricated in the logic layer as described herein.

Turning now to FIG. 5B, one example of an integrated circuit 540 a configured to implement copy data in a third dimensional memory array 502 a includes writing write data 538 to a data area in some planes in the memory 502 a such as layer 3 511 d and layer 1 511 b and writing copy data in different planes in the array 502 a such as duplicating (i.e., copying) the data in layer 3 511 d as copy data in layer 2 511 c and duplicating the data in layer 1 511 b as copy data in layer 0 511 a. In that there can be n memory planes in array 502 a, it may be desirable to separate the plane for a data area from the plane of the copy data for that data area by at least one plane. As one example, data in layer n can be copied in layer 2 511 c such that layer n is separated from its copy layer by at least one memory plane and data in layer 3 511 d can be copied in layer 0 511 a such that layer 3 511 d is separated from layer 0 511 a by at least one memory plane. The separation of data area plane from its respective copy area plane can provide a degree of separation from failures in the array 502 a. In FIG. 5B, separate column drivers 518 a-518 d and separate row drivers 520 a-520 d are operative to activate the appropriate column and row conductive array lines for the plane of the data area and the plane of the copy area such that the write data 538 is written to the data area and to the copy area. During a read data operation, data from the copy area and from the data area can be sensed by separate sense amps 534 a and 534 b and routed to a MUX (not shown). A select signal on the MUX can determine if the read data from the copy area or read data from the data area is to be driven onto a data bus (not shown). For example, if the data from the data area is determined by circuitry and/or algorithms (e.g., ECC or CRC) to be corrupted, then the MUX can be directed to select the data from the copy area for read out on the data bus. Data from the corrupted data area can be re-written with the non-corrupted data from the copy area. ECC or CRC can be accomplished using the aforementioned error detection module.

Moving on to FIG. 5C, an integrated circuit 540 b includes duplicated decoder logic for the row and column decoders such that column decoding is implemented with two column decoders 514 a and 514 b and row decoding is implemented with two row decoders 512 a and 512 b and address 510 is electrically coupled with those decoders. Consequently, even greater protection of data is afforded by circuit 540 b because there are essentially two sets of arrays, the copy data arrays (e.g., in planes layer 0 511 a and layer 2 511 c) and the read data arrays (e.g., in planes layer 3 511 d and layer 1 511 b) that are simultaneously or nearly simultaneously operable to have data read from them or written to them off of one interface. As was described above in reference to FIG. 5B, separate column drivers 518 e-518 h and separate row drivers 520 e-520 h are operative to activate the appropriate column and row conductive array lines for the plane of the data area and copy area such that the write data 538 is written to the data area and to the copy area. During a read data operation, data from the copy area and from the data area can be sensed by separate sense amps 534 a and 534 b and routed to a MUX (not shown) as was described above. In some applications, it may be desirable to separate the plane for a data area from the plane of the copy data for that data area by at least one plane as described in regards to FIG. 5B.

FIG. 6 depicts a detailed illustration of an exemplary parity module, according to one or more embodiments of the invention. Here, parity module 600 includes a partitioned memory array 650 including original data area 602 and copied data area 604, a sense amplifier 610, a sense amplifier 612, a multiplexer (“MUX”) 616, and a parity tree 614. Parity module 600 can be configured to perform a comparison between data read from original data area 602 and copied data area 604. This comparison can be performed simultaneously (or substantially simultaneously), in order to detect any mismatch. To illustrate, partitioned memory array 650 provides two independent data areas containing duplicate sets of data. After reading from partitioned memory array 650, data from each partitioned is driven by a sense amplifier (e.g., sense amplifier 610, sense amplifier 612) to the next state of the data path. Note that this operation can be performed following (or immediately following) any write operation. In some examples, a non-parity read operation (i.e., no comparison of data) can provide data from partitioned memory array 650 to MUX (i.e., multiplexer) 616, and therefore, bypassing any parity check performed by parity tree 614. In other examples, a parity check can be performed, in addition to, forwarding data to MUX 616, in which error flag 630 can be provided, in connection with, read data 620. Parity tree 614 can be configured to perform a comparison on a cycle-by-cycle basis (i.e., each bit is read and compared), and therefore, can guarantee the quality of read data 620. In still other examples, parity tree 614 can perform bit comparison using a variety of algorithms, including but not limited to, cyclic redundancy check (“CRC”) and error-correcting code (“ECC”), all of which can constitute a hash function to detect and correct errors in data. Further, if an error is detected by parity tree 614, error flag 630 can be asserted to a high voltage (e.g., logic value “1”, +V), in addition to, having parity tree 614 divert an instruction to recover the original data by reduplication, and therefore, performing an additional write operation to partition memory array 650. This process can be performed until parity tree 614 detects no further mismatches between the data from original data area 602 and copied data area 604. In some examples, parity module 600 and the above-described elements (i.e., all elements shown and indicated by reference numerals above) can be implemented differently in design, operation, and configuration, and are not limited to the descriptions provided herein. Parity module 600 can be used to implement the aforementioned error detection module.

FIG. 7A depicts an example of arrayed memory cells according to various embodiments of the invention. In this example, a memory cell 700 includes a memory element 702 and NOD 731 positioned above or below (not shown) the memory element 702. The NOD 731 is optional and some configurations of the memory cell 700 will not use the NOD 731. The memory element 702 can include the above mentioned CMO layer(s) and electronically insulating layer (e.g., a thin film layer YSZ having a thickness of approximately 50 Å or less) denoted as 720 and 721 respectively. The layers 720 and 721 can be discrete layers as depicted or they can be continuous and un-etched layers (not shown) as described above. Memory cell 700 further includes terminals 704 and 706 with the memory element electrically in series with the terminals (704, 706). Terminals 704 and 706 can be electrically coupled with or can be formed as electrodes 774 and 778. The electrodes (774, 778) can be made from an electrically conductive material including, but not limited to, platinum (Pt), gold (Au), silver (Ag), iridium (Ir), iridium oxide (IrO_(x)), ruthenium (Ru), palladium (Pd), aluminum (Al), alloys of those materials, and the like. The electrodes (774, 778) can be in contact with and/or electrically coupled with conductive array lines operative to apply the aforementioned voltages for data operations, such as read voltages and write voltages (e.g., program and erase voltages) across one or more selected memory cells 700. The memory element 702 and NOD 731 are electrically in series with each other and electrically in series with the electrodes (774, 778).

Memory cell 700 can be formed between conductive array lines, such as array lines 762 and 760. Thus, memory cell 700 can be formed in an array of other memory cells 700. In FIG. 7A, array lines 762′ and 760′ are depicted in heavy line to illustrate that those array lines have voltages for data operations applied to them such that memory cell 700′ is the selected memory cell for the data operation. The array can be the cross-point array 770 including groups of conductive array lines 760 and 762. For example, array lines 760 can be electrically coupled with the electrodes 774 of the memory cells 700 and/or may be in contact with a surface 774 s of the electrodes 774, and array lines 762 can be electrically coupled with the electrodes 778 of the memory cells 700 and/or may be in contact with a surface 778 s of the electrodes 778. Although not depicted in FIG. 7A, the active circuitry that applies the voltages for data operations is positioned below the array 770 on a substrate (e.g., logic layer 119, 330, or 410) with the array 770 fabricated directly on top of the substrate and the array 770 in contact with the substrate.

FIG. 7B depicts an integrated circuit including memory cells disposed in a single layer or in multiple layers of memory, according to various embodiments of the invention. In this example, integrated circuit 780 is shown to include either multiple layers 750 of memory (e.g., layers 752 a, 752 b, . . . 752 n) or a single memory layer 751 (e.g., layer 752) formed on a base layer 754 with the base layer 754 serving as the logic layer for the array(s) fabricated above it. As will be described in greater detail below, the layers 754 and 752 a, 752 b, . . . 752 n or layers 754 and 752 are not physically separate layers as depicted in FIG. 7B for purposes of illustration, rather they are different portions of a unitary die 800 (not shown) comprised of a FEOL portion for the base layer 754 and a BEOL portion for the layer 752 or layers 752 a, 752 b, . . . 752 n. In at least some embodiments, each layer (e.g., layer 752 or layers 752 a, 752 b, . . . 752 n) of memory can be a cross-point memory array 770 including conductive array lines 760 and 762 arranged in different directions (e.g., orthogonal to each other) to access re-writable memory cells 700 such as two-terminal memory cells as described above. Examples of conductive array lines include X-line conductive array lines (e.g., 760) and Y-line conductive array lines (e.g., 762). The X and Y conductive array lines are sometimes referred to as row lines and column lines respectively. Base layer 754 can include a bulk semiconductor substrate (e.g., a silicon wafer) upon which memory access circuits 753 for performing data operations (e.g., read operations and write operations including the writing copy data) on the memory cells 700 in memory 750 or 751 are fabricated. Base layer 754 may include other circuitry that may or may not be related to data operations on memory. Base layer 754 and circuitry 753 (e.g., CMOS active circuitry such as decoders, drivers, sense amps, buffer, registers, etc.) can be formed in a front-end-of-the-line (FEOL) fabrication process and multiple memory layers 750 or single memory layer 751 can be formed in a back-end-of-the-line (BEOL) fabrication process tailored to fabricating layer(s) of memory arrays on top of the base layer 754. Although not depicted, the base layer 754 can include an inter-level interconnect structure configured to include nodes (e.g., openings in a dielectric material or electrically conductive structures such as vias, plugs, thrus, damascene structures, etc.) for facilitating electrical coupling between the circuitry 753 and the conductive array lines (760, 762) of the array(s) so that signals (e.g., read and write voltages) for data operations (e.g., read and write operations) are electrically communicated between the array(s) and the circuitry 753. The inter-level interconnect structure can be one of the last microelectronic structures fabricated during the FEOL processing.

Moving on to FIG. 7C, where a vertically stacked array 790 includes a plurality of memory layers A,B,C, and D with each memory layer including memory cells 700 a, 700 b, 700 c, and 700 d. Although only four layers are depicted, the array 790 can include fewer layers or can include additional layers up to an nth layer. The array 790 includes three levels of x-direction conductive array lines 710 a, 710 b, and 710 c, and two levels of y-direction conductive array lines 712 a, and 712 b. Unlike the configuration for array 770 in FIG. 7A, the memory cells 700 a, 700 b, 700 c, and 700 d depicted in FIG. 7C share conductive array lines with other memory cells that are positioned above, below, or both above and below that memory cell. The conductive array lines, the memory cells, dielectric materials that electrically isolate structures in the array 790 (not shown), and other structures in the array 790 are formed BEOL above the base layer 754 (not shown) as indicated by +Z on the Z-axis above the dashed line at origin 0; whereas, the active circuitry for performing data operations on the array 790 and the interconnect structure for electrically coupling the active circuitry with the array 790 (e.g., the conductive array lines) are previously formed FEOL as indicated by −Z on the Z-axis below the dashed line at origin 0. Accordingly, the BEOL structure for array 790 is formed on top of the FEOL structure for base layer 754 with the order of fabrication going in a direction from −Z (i.e., FEOL) to +Z (i.e., BEOL) along the Z-axis.

Reference is now made to FIG. 8A, where integrated circuit 780 includes the base layer 754 and active circuitry 753 fabricated on the base layer 754 (e.g., a silicon Si wafer). The integrated circuit 780 is comprised of a single unitary die 800 having a first portion (i.e., the base layer 754) fabricated first using FEOL processing and a second portion (i.e., the single memory layer 752) fabricated second and formed directly on top of the base layer 754 using BEOL processing, such that the second portion is integrally formed with the first portion and completes the formation of the die 800. As one example, the base layer 754 can be a silicon (Si) wafer and the active circuitry 753 can be microelectronic devices formed on the base layer 754 using a CMOS fabrication process. The memory cells 700 and their respective conductive array lines (760, 762) can be fabricated on top of the active circuitry 754 in the base layer 754. Those skilled in the art will appreciate that an inter-level interconnect structure (not shown) can electrically couple the conductive array lines (760, 762) with the active circuitry 753 which may include several metal layers. For example, vias can be used to electrically couple the conductive array lines (760, 762) with the active circuitry 753. The active circuitry 753 may include but is not limited to address decoders, sense amps, memory controllers, data buffers, direct memory access (DMA) circuits, voltage sources for generating the read and write voltages, just to name a few. Active circuits 810-818 can be configured to apply the select voltage potentials (e.g., read and write voltage potentials) to selected conductive array lines (760′, 762′). Moreover, the active circuitry 753 may be electrically coupled with the conductive array lines (760′, 762′) to sense a read current I_(R) that flows through selected memory cells 700′ during a read operation and the read current I_(R) can be sensed and processed by the active circuitry 753 to determine the conductivity profiles (e.g., the resistive state) of the selected memory cells 300′. Examples of conductivity profiles include but are not limited to a programmed conductivity profile written to a memory cell 700′ during a programming data operation and an erased conductivity profile written to a memory cell 700′ during an erase data operation. Memory cells 700 can store data as a plurality of conductivity profiles that can include the programmed or erased conductivity profiles only (e.g., only 1-Bit of data stored per memory cell 700) or more than two conductivity profiles for storing multiple bits of data per memory cell 700 (e.g., two or more bits of data per memory cell 700). The direction of current flow for the read current I_(R) will depend on a magnitude and polarity of a read voltage applied across terminals 704 and 706. In some applications, it may be desirable to prevent un-selected array lines (760, 762) from floating. The active circuits 753 can be configured to apply an un-select voltage potential (e.g., approximately a ground potential) to the un-selected array lines (760, 762). A dielectric material 811 (e.g., SiO₂) may be used where necessary to provide electrical insulation between elements of the integrated circuit 780.

Moving now to FIG. 8B, an integrated circuit 780 includes a plurality of non-volatile memory arrays that are vertically stacked above one another (e.g., along a +Z axis) and are positioned above the base layer 754 that includes the active circuitry 753. The integrated circuit 780 includes vertically stacked memory layers A and B and may include additional memory layers up to an nth memory layer. The memory layers A, B, . . . through the nth layer can be electrically coupled with the active circuitry 753 in the base layer 754 by an inter-level interconnect structure as was described above. Layer A includes memory cells 700 a and first and second conductive array lines (760 a, 762 a), Layer B includes memory cells 700 b and first and second conductive array lines (760 b, 762 b), and if the nth layer is implemented, then the nth layer includes memory cells 700 n and first and second conductive array lines (760 n, 762 n). Dielectric materials 825 a, 825 b, and 825 n (e.g., SiO₂) may be used where necessary to provide electrical insulation between elements of the integrated circuit 820. Active circuits 840-857 can be configured to apply the select voltage potentials (e.g., read and write voltage potentials) to selected conductive array lines (e.g., 760 a, b, . . . n, and 762 a, b, . . . n). Driver circuits 850 and 857 are activated to select conductive array lines 760′ and 762′ to select memory cell 700 b′ for a data operation. As was described above, the active circuits 753 can be used to sense the read current I_(R) (not shown) from selected memory cells 700 b′ during a read operation and can be configured to apply the un-select voltage potential to the un-selected array lines. As described above, the integrated circuit 780 comprises the die 800 that is a unitary whole comprised of a FEOL circuitry portion fabricated on base layer 754 and a BEOL memory portion having multiple memory layers that is in contact with the FEOL portion and is fabricated directly on top of the FEOL portion.

In FIG. 8C, an integrated circuit 780 includes base layer 754, active circuitry 753, and vertically staked memory layers A, B, C, and D that are fabricated above the base layer 754. Active circuits 840-857 are configured to perform data operations on the vertically staked memory layers A, B, C, and D. Driver circuits 844 and 857 are activated to select memory cell 700 a′ for a data operation and driver circuits 842 and 848 are activated to select memory cell 700 d′ for a data operation. A dielectric layer 851 is operative to electrically isolate the various components of integrated circuit 780. As described above, the integrated circuit 780 comprises the die 800 that is a unitary whole comprised of a FEOL circuitry portion fabricated on base layer 754 and a BEOL memory portion having multiple memory layers that is in contact with the FEOL portion and is fabricated directly on top of the FEOL portion.

Moving on to FIG. 9, an exemplary memory system 900 includes the aforementioned non-volatile two-terminal cross-point memory array 770 (array 770 hereinafter) and the plurality of first conductive and second conductive traces denoted as 760 and 762, respectively. The memory system 900 also includes an address unit 903 and a sense unit 905. The address unit 903 receives an address ADDR, decodes the address, and based on the address, selects at least one of the plurality of first conductive traces (denoted as 760′) and one of the plurality of second conductive traces (denoted as 762′). The address unit 903 applies select voltage potentials (e.g., read or write voltages) to the selected first and second conductive traces 760′ and 762′. The address unit 903 also applies a non-select voltage potential to unselected traces 760 and 762. The sense unit 905 senses one or more currents flowing through one or more of the conductive traces. During a read operation to the array 770, current sensed by the sense unit 905 is indicative of stored data in a memory cell 700′ positioned at an intersection of the selected first and second conductive traces 760′ and 762′. A bus 921 coupled with an address bus 923 can be used to communicate the address ADDR to the address unit 903. The sense unit 905 processes the one or more currents and at least one additional signal to generate a data signal DOUT that is indicative of the stored data in the memory cell. In some embodiments, the sense unit 905 may sense current flowing through a plurality of memory cells and processes those currents along with additional signals to generate a data signal DOUT for each of the plurality of memory cells. A bus 927 communicates the data signal DOUT to a data bus 929. During a write operation to the array 770, the address unit 903 receives write data DIN to be written to a memory cell specified by the address ADDR. A bus 925 communicates the write data DIN from the data bus 929 to the address unit 903. The address unit 903 determines a magnitude and polarity of the select voltage potentials to be applied to the selected first and second conductive traces 760′ and 762′ based on the value of the write data DIN. For example, one magnitude and polarity can be used to write a logic “0” and a second magnitude and polarity can be used to write a logic “1”. In other embodiments, the memory system 900 can include dedicated circuitry that is separate from the address unit 903 to generate the select potentials and to determine the magnitude and polarity of the select potentials.

One skilled in the art will appreciate that the memory system 900 and its components (e.g., 903 and 905) can be electrically coupled with and controlled by an external system or device (e.g., a microprocessor or a memory controller). Optionally, the memory system 900 can include at least one control unit 907 operative to coordinate and control operation of the address and sense units 903 and 905 and any other circuitry necessary for data operations (e.g., read and write operations) to the array 770. Although only one array 770 is depicted, the array 770 can comprise a single layer of memory (e.g., 752) or multiple layers of vertically stacked memory (752 a, 752 b, . . . 752 n) as depicted in FIGS. 7A-8C. One or more signal lines 909 and 911 can electrically couple the control unit 907 with the address and sense units 903 and 905. The control unit 907 can be electrically coupled with an external system (e.g., a microprocessor or a memory controller) through one or more signal lines 913.

As was described above in reference to FIGS. 7A through 8C, one or more of the arrays 770 can be positioned over a substrate 754 that includes active circuitry 753 and the active circuitry 753 can be electrically coupled with the array(s) 770 using an interconnect structure that couples signals from the active circuitry 753 with the conductive array lines 760 and 762. In FIG. 9, the busses, signal lines, control signals, the address, sense, and control units 903, 905, and 907 can comprise the active circuitry 753 and its related interconnect, and can be fabricated FEOL on the substrate 754 (e.g., a silicon wafer) using a microelectronics fabrication technology, such as CMOS, for example. The circuitry, busses, and control signals depicted in FIG. 9 can implement the circuitry (e.g., FEOL circuitry in the logic layers depicted in FIGS. 1-6) and the array 770 can be used to implement the multiple memory layers (e.g., BEOL memory planes in FIGS. 1-6).

Although FIGS. 7B and 8A depict single layer arrays, the BEOL memory can be configured to have a plurality of separate arrays on a single plane with some of the plurality of arrays used for the data area (e.g., data area 602) and other of the plurality of arrays used for the copy area (e.g., copy area 604). In this configuration, the arrays for the data area and the copy area are disposed on the same memory plane in horizontal relationship to one another (see FIG. 3C). Therefore, the configurations depicted in FIGS. 1-6 need not be restricted to vertical only configurations of data and copy memory. The BEOL memory can be flexibly configured into horizontal only configurations, vertically stacked configurations (e.g., FIGS. 3A-5C), or a combination of both horizontal and vertical configurations. In applications that require a small amount of data storage with redundancy to protect data integrity, it may be more efficient to implement the storage for the data area and the copy area in a single layer or plane of memory in which the aforementioned plurality of horizontally disposed separate arrays are used. On the other hand, for large data storage requirements such as in RAID systems and SSD, it may be more efficient to use the vertically stacked memory planes for the data area and the copy area with some planes being used as the copy area for the copy data only and other planes being used as the data area for the data as was described above.

Reference is now made to FIG. 10, where an electrical system 1000 includes a CPU 1001 that is electrically coupled 1004 with a bus 1002, an I/O unit 1007 that is electrically coupled 1010 with the bus 1002, and a storage unit 1005 that is electrically coupled 1008 with the bus 1002. The I/O unit 1007 is electrically coupled 1012 to external sources (not shown) of input data and output data. The CPU 1001 can be any type of processing unit including but not limited to a microprocessor (μP), a micro-controller (μC), and a digital signal processor (DSP), for example. Via the bus 1002, the CPU 1001, and optionally the I/O unit 1007, performs data operations (e.g., reading and writing data) on the storage unit 1005. The storage unit 1005 stores at least a portion of the data in the aforementioned non-volatile two-terminal cross-point array as depicted in FIGS. 7A through 8C. Each memory array includes a plurality of the two-terminal memory cells 700. The configuration of the storage unit 1005 will be application specific. Example configurations include but are not limited to one or more single layer non-volatile two-terminal cross-point arrays (e.g., 752) and one or more vertically stacked non-volatile two-terminal cross-point arrays (e.g., 752 a-752 n). In the electrical system 1000, data stored in the storage unit 1005 is retained in the absence of electrical power. The CPU 1001 may include a memory controller (not shown) for controlling data operations to the storage unit 1005.

Alternatively, the electrical system 1000 may include the CPU 1001 and the I/O unit 1007 coupled with the bus 1002, and a memory unit 1003 that is directly coupled 1006 with the CPU 1001. The memory unit 1003 is configured to serve some or all of the memory needs of the CPU 1001. The CPU 1001, and optionally the I/O unit 1007, executes data operations (e.g., reading and writing data) to the non-volatile memory unit 1003. The memory unit 1003 stores at least a portion of the data in the aforementioned non-volatile two-terminal cross-point array as depicted in FIGS. 7A through 8C. Each memory array can include a plurality of the two-terminal memory cells 700 with each memory cell 700 including the two-terminal memory element 702 and NOD 731. The configuration of the memory unit 1003 will be application specific. Example configurations include but are not limited to one or more single layer non-volatile two-terminal cross-point arrays (e.g., 752) and one or more vertically stacked non-volatile two-terminal cross-point arrays (e.g., 752 a-752 n). In the electrical system 1000, data stored in the memory unit 1003 is retained in the absence of electrical power. Data and program instructions for use by the CPU 1001 may be stored in the memory unit 1003. The CPU 1001 may include a memory controller (not shown) for controlling data operations to the non-volatile memory unit 1003. The memory controller may be configured for direct memory access (DMA). Storage 1005 and/or non-volatile memory unit 1003 can implement data redundancy as described herein.

Reference is now made to FIG. 11, where a top plan view depicts a single wafer (denoted as 1170 and 1170′) at two different stages of fabrication: FEOL processing on the wafer denoted as 1170 during the FEOL stage of processing where active circuitry 753 is formed; followed by BEOL processing on the same wafer denoted as 1170′ during the BEOL stage of processing where one or more layers of non-volatile memory are formed. Wafer 1170 includes a plurality of the base layer die 754 (see FIGS. 1, 3A-4, and 7B-8C) formed individually on wafer 1170 as part of the FEOL process. As part of the FEOL processing, the base layer die 754 may be tested 1172 to determine their electrical characteristics, functionality, performance grading, etc. After all FEOL processes have been completed, the wafer 1170 is optionally transported 1104 for subsequent BEOL processing (e.g., adding one or more layers of memory such as single layer 752 or multiple layers 752 a, 752 b, . . . 752 n) directly on top of each base layer die 754. A base layer die 754 is depicted in cross-sectional view along a dashed line FF-FF where the substrate the die 754 is fabricated on (e.g., a silicon Si wafer) and its associated active circuitry are positioned along the −Z axis. For example, the one or more layers of memory are grown directly on top of an upper surface 754 s of each base layer die 754 as part of the subsequent BEOL processing.

During BEOL processing the wafer 1170 is denoted as wafer 1170′, which is the same wafer subjected to additional processing to fabricate the memory layer(s) directly on top of the base layer die 754. Base layer die 754 that failed testing may be identified either visually (e.g., by marking) or electronically (e.g., in a file, database, email, etc.) and communicated to the BEOL fabricator and/or fabrication facility. Similarly, performance graded base layer die 754 (e.g., graded as to frequency of operation) may identified and communicated to BEOL the fabricator and/or fabrication facility. In some applications the FEOL and BEOL processing can be done by the same fabricator or performed at the same fabrication facility. Accordingly, the transport 1104 may not be necessary and the wafer 1170 can continue to be processed as the wafer 1170′. The BEOL process forms the aforementioned memory layer(s) directly on top of the base layer die 754 to form a finished die 800 that includes the FEOL circuitry portion 754 along the −Z axis and the BEOL memory portion along the +Z axis (see FIGS. 7B-8C). A cross-sectional view along a dashed line BB-BB depicts a memory device die 800 with a single layer of memory 752 grown directly on top of base die 754 along the +Z axis, and alternatively, another memory device die 800 with three vertically stacked layers of memory 752 a, 752 b, and 752 c grown directly on top of base die 754 along the +Z. Finished die 800 on wafer 1170′ may be tested 1174 and good and/or bad die identified. Subsequently, the wafer 1170′ can be singulated 1178 to remove die 800 (e.g., die 800 are precision cut or sawed from wafer 1170′) to form individual memory device die 800. The singulated die 800 may subsequently be packaged 1179 to form integrated circuits 1190 for mounting to a PC board or the like, as a component in an electrical system (not shown). Here a package 1181 can include an interconnect structure 1187 (e.g., pins, solder balls, or solder bumps) and the die 800 mounted in the package 1181 and electrically coupled 1183 with the interconnect structure 1187 (e.g., using wire bonding). The integrated circuits 1190 (IC 1190 hereinafter) may undergo additional testing 1185 to ensure functionality and yield. One or more of the IC's 1190 can be used in a data storage system such as a RAID storage system in which the non-volatile memory in the one or more layers of memory in each IC 1190 is used to replace or supplant HDD's in the RAID system. Unlike FLASH non-volatile memory, the IC's 1190 do not require an erase operation prior to a write operation so the latency associated with the erase operation is eliminated and the latency associated with FLASH OS and/or FLASH file system required for managing the erase operation is eliminated. Another application for the IC's 1190 is as a replacement for conventional FLASH-based non-volatile memory in SSD's. Here, one or more of the IC's 1190 can be mounted to a PC board along with other circuitry and placed in an appropriate enclosure to implement a SSD that can be used to replace a HDD. As mentioned above, the IC's 1190 do not require the erase before write operation and it associated latency and overhead. For both RAID and SSD applications, the vertically stacked memory arrays allow for increases in storage density without increasing die size because the memory arrays are fabricated above their associated active circuitry so extra memory capacity can be achieved by adding additional layers of memory above the FEOL base layer die 754. The IC 1190 can be used in embedded memory applications in which data redundancy is desirable such as in portable PC's, cell phones, PDA's, image capture devices, and the like.

In general, the devices and methods discussed herein are applicable to semiconductor memory (i.e., material used for data storage) formed and fabricated using various types of materials such as silicon dioxide, silicon oxide, noble metals, conductive metal oxides (e.g., perovskites), and others. Examples of such memories include SRAM, MRAM and FLASH memories, cross-point array (layout) memory and stacked cross-point array memory (e.g., whether single layer non-volatile two-terminal cross-point arrays, or one or more vertically stacked non-volatile two terminal cross arrays), three/third-dimension memory arrays (including those that emulate other types of memory, providing memory combinations within a single component), resistive state memory devices, and memory systems.

The various embodiments of the invention can be implemented in numerous ways, including as a system, a process, an apparatus, or a series of program instructions on a computer readable medium such as a computer readable storage medium or a computer network where the program instructions are sent over optical or electronic communication links. In general, the steps of disclosed processes can be performed in an arbitrary order, unless otherwise provided in the claims.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. In fact, this description should not be read to limit any feature or aspect of the present invention to any embodiment; rather features and aspects of one embodiment can readily be interchanged with other embodiments. Notably, not every benefit described herein need be realized by each embodiment of the present invention; rather any specific embodiment can provide one or more of the advantages discussed above. In the claims, elements and/or operations do not imply any particular order of operation, unless explicitly stated in the claims. It is intended that the following claims and their equivalents define the scope of the invention. 

1. An apparatus, comprising: a substrate; a first subset of memory cells in multiple memory layers configured to store data; a second subset of memory cells in the multiple memory layers configured to store a copy of the data, the first and second subsets of the multiple memory layers are in contact with the substrate and are fabricated directly above the substrate; and active circuitry fabricated on the substrate and positioned below the multiple memory layers, the active circuitry including a redundancy circuit electrically coupled with the first subset of memory cells and the second subset of memory cells, the redundancy circuit configured to access the first subset of memory cells to store the data and to access the second subset of memory cells to store the copy of the data, wherein any of the multiple memory layers is configured to include the first subset of memory cells and the second subset of memory cells.
 2. The apparatus of claim 1, wherein the active circuitry includes a control module configured to write the data to the first subset of memory cells, and to write the copy of the data to the second subset of memory cell, wherein the copy of the data is written substantially simultaneously to the multiple memory layers.
 3. The apparatus of claim 1, wherein the active circuitry includes a control module configured to write the data to the first subset of memory cells and to write the copy of the data to the second subset of memory cell without an erase operation that precedes the writing of the data or the writing of the copy of the data.
 4. The apparatus of claim 1, wherein the first subset of memory cells and the second subset of memory cells further comprises memory cells configured to store data as a plurality of conductivity profiles that are retained in the absence of power.
 5. The apparatus of claim 1 and further comprising: interleaved layers of memory in the multiple memory layers, wherein layers of memory to store the copy of the data are interleaved with layers of memory to store the data.
 6. The apparatus of claim 1 and further comprising: at least two layers including the first subset of memory cells to store the data; and at least one layer including the second subset of memory cells to store the copy of the data, wherein the at least one layer including the second subset of memory cells is between the at least two layers including the first subset of memory cells.
 7. The apparatus of claim 1, wherein the active circuitry includes a first subset of drivers configured to access the first subset of memory cells in a first subset of the multiple memory layers, and a second subset of drivers configured to access the second subset of memory cells in a second subset of the multiple memory layers.
 8. The apparatus of claim 7, wherein the active circuitry includes a first decoder coupled electrically coupled with the first subset of drivers and with the second subset of drivers, wherein the first decoder is configured to provide data to the first subset of drivers and the second subset of drivers.
 9. The apparatus of claim 7, wherein the active circuitry includes first decoder electrically coupled with the first subset of drivers, and a second decoder electrically coupled with the second subset of drivers, wherein the first decoder and the second decoder are configured to provide data to the first subset of drivers and the second subset of drivers, respectively.
 10. The apparatus of claim 1, wherein the active circuitry includes an access selector configured to detect a write operation in association with a portion of the multiple memory layers, and to select whether to suppress generation of the copy of the data.
 11. The apparatus of claim 1, wherein the active circuitry includes an access selector configured to select two layers of the multiple memory layers to respectively access the first subset of memory cells and the second subset of memory cells during a read operation.
 12. The apparatus of claim 1 and wherein the redundancy circuit further comprises an error detection module configured to detect a mismatch between the data in the first subset of memory cells and the copy of the data in the second subset of memory cells.
 13. The apparatus of claim 12, wherein the error detection module is further configured to generate an error flag signal indicating the mismatch.
 14. The apparatus of claim 12, wherein the error detection module is further configured upon detection of the mismatch, to select the copy of the data and to provide the copy of the data as read data.
 15. The apparatus of claim 1, wherein the first subset of memory cells and the second subset of memory cells are configured to be read substantially in parallel to compare the data and the copy of the data, respectively.
 16. An integrated circuit, comprising: a substrate including active circuitry fabricated on the substrate; a first memory block fabricated directly above the substrate and configured to store a datum, the first memory block including a memory cell configured to store the datum based on a conductivity profile of the memory cell; a second memory block fabricated directly above the substrate and configured to store a duplicate of the datum, the second memory block including another memory cell configured to store the datum based on a conductivity profile of the another memory cell; and a redundancy circuit included in the active circuitry and positioned below the first and second memory blocks, the redundancy circuit electrically coupled with the first and the second memory blocks, the redundancy circuit configured to duplicate the datum and to write the datum to both the first memory block and the second memory block.
 17. The integrated circuit of claim 16, wherein the redundancy circuit further comprises a controller configured to detect a mismatch between the datum and the duplicate of the datum, and to recover the datum.
 18. The integrated circuit of claim 16, wherein the redundancy circuit is configured to duplicate the datum by generating one or more copies of the datum and to store the one or more copies of the datum within the second memory block.
 19. The integrated circuit of claim 16, wherein the memory cell and the another memory cell comprise third dimension memory cells.
 20. The integrated circuit of claim 16 and further comprising: a single layer of memory wherein the first memory block and the second memory block reside in the single layer or memory.
 21. The integrated circuit of claim 16 and further comprising: two or more layers of memory, wherein the first memory block and the second memory block reside in separate layers of the two or more layers of memory.
 22. The integrated circuit of claim 16, wherein the redundancy circuit includes a portion of a memory layer being configured to store wait-state data associated with a recovery operation.
 23. The integrated circuit of claim 16, wherein the active circuitry further includes an access selector configured to detect a write operation in association with a portion of the first memory block and operative to select whether to suppress duplication of the datum in the second memory block.
 24. A method for non-volatile data redundancy, comprising: writing data substantially simultaneously to at least two blocks of non-volatile memory in an array of resistance-based memory cells that are fabricated directly above a substrate including active circuitry fabricated on the substrate and configured to perform data operations on the array; storing the data in the at least two blocks of non-volatile memory; and comparing the data stored in the at least two blocks of non-volatile memory to detect a mismatch by reading the data from the at least two blocks of non-volatile memory substantially simultaneously.
 25. The method of claim 24 and further comprising initiating a recovery operation to reduplicate the data in at least one of the two blocks of non-volatile memory. 